This device presents textual information about PC hardware and
allows user–level control of the I/O ports on x86–class and DEC
Reads from cputype recover the processor type and clock rate in
MHz. Reads from cputemp recover one line containing per processor
containing two fields: the processor temperature and precision
in degrees Celsius. Reads from archctl yield at least data of
Where AMD64 is the processor type, 2201 is the processor speed
in MHz, and pge is present only if the `page global extension'
capability is present; the next line reflects its setting. coherence
is followed by one of mb386, mb586, mfence or nop, showing the
form of memory barrier used by the kernel.
cmpswap is followed by cmpswap386 or cmpswap486, reflecting the
form of `compare and swap' used by the kernel. i8253set is a flag,
indicating the need to explicitly set the Intel 8253 or equivalent
timer. There may be lines starting with cache that reflect the
state of memory caching via MTRRs (memory–
type region registers). The second word on the line is default
or a C–style number which is the base physical address of the region;
the third is a C–style length of the region; and the fourth is
one of uc (for uncachable), wb (write–back), wc (write–combining),
wp (write–protected), or wt (write–through). A region
may be a subset of another region, and the smaller region takes
precedence. This may be used to make I/O registers uncachable
in the midst of a write–combining region mostly used for a video
framebuffer, for example. Control messages may be written to archctl
and use the same syntax as the data read from
archctl. Known commands include cache, coherence, i8253set, and
Reads from ioalloc return I/O ranges used by each device, one
line per range. Each line contains three fields separated by white
space: first address in hexadecimal, last address, name of device.
Reads from irqalloc return the enabled interrupts, one line per
interrupt. Each line contains six fields separated by white space:
the trap number, the IRQ it is assigned to, the number of interrupts
from this source, the CPU cycles spent servicing this interrupt,
the type of interrupt, and the name of the device using it.
Interrupt types are architecture dependent.
Reads and writes to iob, iow, and iol cause 8–bit wide, 16–bit wide,
and 32–bit wide requests to I/O ports. The port accessed is determined
by the byte offset of the file descriptor.
The msr file allows model–specific registers to be read and written
with the same protocol as iob. MSR registers are 8 bytes on x86
cpu AMD64 2201 pge|
cache default uc
cache 0x0 1073741824 wb
cache 0x3ff00000 1048576 uc